In applications of power transistors, for example metal-oxide-semiconductor field effect transistors (MOSFETs), the heat dissipation and package size are two important parameters of the devices. Device's heat dissipation is improved by exposing the source and/or drain of the transistor, but the implementation process is very complicated.
In some switching circuits, such as synchronous buck converter, half-bridge converter and inverter, two power MOSFETs are needed for switching in a complementary manner. The switching circuit as shown in FIG. 1 includes two MOSFETs, which is HS MOSFET 1 and LS MOSFET 2, connected in series to a voltage source 3, in which, the source of HS MOSFET 1 is connected to the drain of LS MOSFET 2 through a plurality of parasitic inductances such as LDHS, LSHS, LDLS and LSLS.
For these devices, when the HS chip and LS chip are co-packaged and two chips are connected by lead wire, the lead inductance is reduced. However, the HS chip and LS chip are arranged side by side on one side of a lead frame, thus the whole device has a large size.